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[AK4688] ms1420-j-00 2012/05 - 1 - ? a AK4688 x 1 ??a| codec pb{ ob? adc/dac w??????x 24bit ?pw? z?? ??q ??8?^t0 `om?b{?????t0 `h?????x? ?z ?t???? ??t
?dpb{ow????t?? 3.3v wo?op????????w 2vrms ? z?t0 `z ac ??????3?????s?srw? ?z ? ??_nb?\qu pv?b{ AK4688 x adc t 99db z dac t 105db w?????????jz blu-ray ??sr w?????????3a?????)+z?3???3at7&pb{ ? ? ? adc, dac ??8?^0 ? ?????; ???a|??? ? 2ch 24bit adc - 64 |????? - ???? *t
: : 7g 48khz -
?
????????o - s/(n+d): 83db - ??????? , s/n: 99db - |???????;???? hpf ? 2ch 24bit dac - 128 |????? - ???? *t
: : 7g 192khz - 24 ??? 8 ???????? - s/(n+d): 95db - ??????? , s/n: 105db - ?????3????o ? ??1? ? ?????? : 256fs, 384fs, 512fs 768fs (fs=32khz 48khz) 128fs, 192fs, 256fs 384fs (fs=64khz 96khz) 128fs, 192fs (fs=128khz ~ 192khz) ? 2 ??|???| i/f (port1, port2) - ? / ?t??0 (port1) - i/f ???? :
2g? , ?g? (16bit, 24bit), i 2 s (port1, port2) ? ???? ???? / i 2 c-bus ????0 ? ?o?y : - digital i/o and charge pump: 3.0v 3.6v - adc analog: 3.0v 3.6v - dac analog: 3.0v 3.6v ? ?-? : 36pin qfn AK4688 asynchronous stereo codec with capless line i/o
[AK4688] ms1420-j-00 2012/05 - 2 - 2ch adc cvee cp cn lout rout mclk1 bick1 lrck1 sdto msn port1 2vrms hpf serial i/f 2vrms +/-50mvdc input pwad bit pdn1 pin mclk2 bick2 lrck2 sdti port2 2ch dac serial i/f sda scl control i/f a vdd1 a vss1 a vdd2 a vss2 dvdd dvss vref charge pump de-em lin rin i2c pdn2 pdn1 lo li ri ro cad0/cks pwad/pwda bit pdn1/pdn2 pin pwda bit pdn2 pin figure 1. AK4688 block diagram
[AK4688] ms1420-j-00 2012/05 - 3 - |??????? AK4688en ? 20 +85 c 36pin qfn (0.5mm pitch) akd4688 AK4688 u??` e? ? 36pin qfn (0.5mm pitch) lo li rin nc lin i2c msn sda ro r1 a vdd1 a vss1 a vss2 a vdd2 rout sdto lrck1 bick1 mclk1 pdn1 pdn2 mclk2 bick2 cn cp dvss dvdd test2 test1 cad0 stdi a k4688 top view 28 29 30 31 32 33 34 35 27 26 25 17 16 15 14 13 12 11 10 24 23 22 21 20 1 2 3 4 5 6 7 8 36 19 cvee 18 lrck2 9 vref lout scl
[AK4688] ms1420-j-00 2012/05 - 4 - e??; no. pin name i/o function 1 sdto o audio serial data output pin (for port1) 2 lrck1 i/o channel clock pin (for port1) 3 bick1 i/o audio serial data clock pin (for port1) 4 mclk1 i adc master clock input pin (for port1) 5 pdn1 i power-down mode for adc when ?l?, the adc is powered-down. 6 pdn2 i power-down mode for dac when ?l?, the dac is powered-down. 7 mclk2 i dac master clock input pin (for port2) 8 bick2 i audio serial data clock pin (for port2) 9 lrck2 i input channel clock pin (for port2) 10 sdti i audio serial data input pin (for port2) cad0 i cad address pin (i2c pin = ?h?) 11 cks i adc mclk speed select pin (i2c pin = ?l?) ?h?: mclk=768fs, ?l?: mclk=256fs 12 test1 i this pin must be connected to the ground 13 test2 i this pin must be connected to the ground 14 dvdd - digital power supply pin, 3.0v 3.6v 15 dvss - digital ground pin, 0v 16 cp i positive charge pump capacitor terminal pin (for analog input/output) 17 cn i negative charge pump capacitor terminal pin (for analog input/output) 18 cvee o charge pump circuit negative voltage output pin (for analog input/output) 19 rout o rch analog output pin 20 lout o lch analog output pin 21 vref o reference output pin connect to avss2 with a 1f low esr capacitor over all temperatures. 22 avdd2 - dac analog power supply pin, 3.3v 3.6v 23 avss2 - adc analog ground pin, 0v 24 avss1 - adc analog ground pin, 0v 25 avdd1 - adc analog power supply pin, 3.0v 3.6v 26 ri o rch feedback resistor input pin 27 ro o rch feedback resistor output pin 28 lo o lch feedback resistor output pin 29 li o lch feedback resistor input pin 30 rin i rch input pin 31 nc - this pin must be connected to the ground 32 lin i lch input pin 33 i2c i i 2 c pin ?h?= i 2 c control, ?l?= h/w control 34 sda i/o control data pin (i2c pin = ?h?) when the i2c pin = ?l? (h/w control), the sda pin must be connected to dvss. 35 scl i control data clock pin (i2c pin = ?h?) when the i2c pin = ?l? (h/w control), the scl pin must be connected to dvss. 36 msn i port1 master mode select pin. ?l?(connected to the ground): slave mode. ?h?(connected to dvdd) : master mode. note: ??????`?????
[AK4688] ms1420-j-00 2012/05 - 5 -
?07g (avss1=avss2=dvss =0v; note 1 ) parameter symbol min max unit power supply dvdd avdd1 avdd2 -0.3 -0.3 -0.3 4.0 4.0 4.0 v v v input current (any pins except for supplies) iin - 10 ma digital input voltage (mclk1-2, pdn1-2, lrck1-2, sdti, bick1-2, sda, scl, msn, cad0 pins ) vind -0.3 dvdd+0.3 v analog input voltage (lin, rin pins) vina -0.3 avdd1+0.3 v ambient operating temperature ta -20 85 c storage temperature tstg -65 150 c note 1. avss1, avss2, dvss ??????A ? : ??????????? ????^?
* ??^ e (avss1=avss2=dvss =0v; note 1 ) parameter symbol min typ max unit power supply ( note 2 ) dvdd avdd1 avdd2 3.0 3.0 3.0 3.3 3.3 3.3 3.6 3.6 3.6 v v v note 2. avdd1, avdd2 ??? dvdd ? (avdd1, avdd2) 0.3v ? ? : ?``??d???v??????? ???
[AK4688] ms1420-j-00 2012/05 - 6 - ????
q (ta=25 c; avdd1=avdd2 = dvdd= 3.3v; avss1=avss2=dvss =0v; fs=48khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency = 20hz 20khz at fs=48khz, 20hz~40khz at fs=96khz; 20hz~40khz at fs=192khz, all blocks are synchronized, unless otherwise specified) parameter min typ max unit pre-amp characteristics: feedback resistance rf 12 39 92 k input resistance ri 18 47 92 k output level lo / ro pins (adc=0dbfs) ( note 3 ) 1.82 1.91 2.00 vrms load resistance r l ( note 4 ) 18 k load capacitance c l ( note 4 ) 20 pf analog input (lin, rinpin) to adc analog input characteristics resolution 24 bits s/(n+d) (-1dbfs) fs=48khz - 83 db dr (-60db fs) fs=48khz, a-weighted - 99 db s/n (input off) fs=48khz, a-weighted - 99 db interchannel isolation ( note 5 ) - 100 db interchannel gain mismatch 0 - db gain drift 50 - ppm/ c power supply rejection ( note 6 ) 50 db dac to analog output (lout, rout pin) characteristics resolution 24 bits s/(n+d) (0dbfs) fs=48khz fs=96khz fs=192khz - - - 95 93 93 db db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz, a-weighted fs=192khz, a-weighted - - - 105 105 105 db db db s/n (?0? data) fs=48khz, a-weighted fs=96khz, a-weighted fs=192khz, a-weighted - - - 105 105 105 db db db interchannel isolation - 100 db interchannel gain mismatch 0 - db dc offset (at output pin) ?5 0 +5 mv gain drift 50 - ppm/ c output voltage lout/rout= 2 x avdd2/3.3 1.85 2 2.15 vrms load resistance 5 k load capacitance (c1) 30 pf power supply rejection ( note 6 ) 62 db note 3. ?? 47k feedback ? 39k ?? 2.3vrms ?? adc ??` ????? note 4. lo/ro pin ?????r???? figure 3 r l c l ? note 5. lin rin g???g`? note 6. avdd1, avdd2, dvdd 1khz, 50mvpp ???
[AK4688] ms1420-j-00 2012/05 - 7 - 470 2.2nf ana log out (c 1) lout/rout AK4688 figure 2. lineout circuit example adc li lo 0v r f r i 0v lin (r l ) (c l ) - + AK4688 figure 3. pre amp ?
[AK4688] ms1420-j-00 2012/05 - 8 - power supplies parameter min typ max unit power supply current normal operation (pdn1 pin = pdn2 pin = ?h?) avvd1 avdd2 dvdd dvdd+avdd1+avdd2 power-down mode (pdn1 pin = pdn2 pin = ?l?; note 7 ) dvdd+avdd1+avdd2 3 11 13 27 1 - - - 40 20 ma ma ma ma a note 7. pdn1-2, test1-2 pins dvss ? ??????? (mclk1-2, bick1-2, lrck1-2, sdti, sda, scl, msn, cad0 pins) dvdd ? dvss ????? msn pin dvdd ?? lrck1, bick1 pin ??B????`?? ?????
q (ta=25 c; avdd1=avdd2 = dvdd= 3.3v; fs=48khz) parameter symbol min typ max unit adc digital filter (decimation lpf): passband ( note 8 ) 0.1db -0.2db -3.0db pb 0 - - 21.1 21.7 18.8 - - khz khz khz stopband sb 28.5 khz stopband attenuation sa 73 db group delay ( note 10 ) gd 17 1/fs group delay distortion gd 0 s adc digital filter (hpf): frequency response ( note 8 ) -3db -0.1db fr 1.0 7.1 hz hz dac digital filter: passband 0.05db ( note 9 ) -6.0db pb 0 - 24.0 21.7 - khz khz stopband ( note 9 ) sb 26.3 khz passband ripple pr 0.05 db stopband attenuation sa 64 db group delay ( note 10 ) gd - 24 - 1/fs de-emphasis filter (dem = on) de-emphasis error (dc ) fs = 32khz fs = 44.1khz fs = 48khz - - - - - - ?1.5/0 ?0.2/+0.2 0/+0.6 db db db dac digital filter + analog filter: (dem = off) frequency response 20.0khz 40.0khz 80.0khz fs=44.1khz fs=96khz fs=192khz fr fr fr - - - 0.2 0.3 1.0 - - - db db db note 8. ?^? fs ?? -0.1db ? 21.8khz 0.454 x fs(dac) ?? 1khz ? note 9. ?^?? fs ( ?????` ) ? pb=0.4535fs(@ 0.05db) sb=0.546fs ? note 10. ????W???????I? 24 ????` port1 ??????rg? dac ????I? 16/24 ????` port2 ???????????rg?
[AK4688] ms1420-j-00 2012/05 - 9 - dc ?
q (ta=25 c; avdd1=avdd2 = dvdd= 3.3v) parameter symbol min typ max unit high-level input voltage low-level input voltage vih vil 70%dvdd - - - - 30%dvdd v v high-level output voltage ( iout=-400 a) low-level output voltage (iout= 400 a(except sda pin), 3ma(sda pin)) voh vol dvdd-0.4 - - - 0.4 v v input leakage current iin - - 10 a ??????
q (ta=25 c; avdd1=avdd2 = dvdd= 3.3v; c l = 20pf (except for sda pin), cb=400pf(sda pin)) parameter symbol min typ max unit master clock timing frequency duty feclk declk 8.192 40 50 36.864 60 mhz % master clock 256fsn, 128fsd: pulse width low pulse width high 384fsn, 192fsd: pulse width low pulse width high 512fsn, 256fsd, 128fsq: pulse width low pulse width high 768fsn, 384fsd, 192fsq: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 8.192 0.37 0.37 12.288 0.37 0.37 16.384 0.37 0.37 24.576 0.37 0.37 12.288 18.432 24.576 36.864 mhz 1/fclk 1/fclk mhz 1/fclk 1/fclk mhz 1/fclk 1/fclk mhz 1/fclk 1/fclk lrck1timing (slave mode) duty cycle fsn duty 32 45 48 55 khz % lrck2timing (slave mode) normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 32 32 128 45 48 96 192 55 khz khz khz % lrck1 timing (master mode) normal speed mode duty cycle fsn duty 32 50 48 khz % power-down & reset timing pdn pulse width ( note 11 ) pdn ? ? to sdto valid ( note 12 ) tpd tpdv 150 2640 ns 1/fs note 11. pdn1, pdn2 pin ????B??? ? ??? ? ?? note 12. pdn1 pin ?? mclk ?????? lrck Q?s 64/fs cvee ? adc ?`??? 528/fs sdtio ?
[AK4688] ms1420-j-00 2012/05 - 10 - parameter symbol min typ max unit audio interface timing (slave mode) port2(dac) bick2 period bick2 pulse width low pulse width high lrck2 edge to bick2 ? ? ( note 13 ) bick2 ? ? to lrck2 edge ( note 13 ) sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tsdh tsds 81 20 20 20 20 10 10 ns ns ns ns ns ns ns port1 (adc) bick1 period bick1 pulse width low pulse width high lrck1 edge to bick1 ? ? ( note 13 ) bick1 ? ? to lrck1 edge ( note 13 ) lrck1 to sdto (msb) bick1 ? ? to sdto tbck tbckl tbckh tlrb tblr tlrs tbsd 324 128 128 80 80 80 80 ns ns ns ns ns ns ns audio interface timing (master mode) bick1 frequency bick1 duty bick1 ? ? to lrck1 edge bick1 ? ? to sdto fbck dbck tmblr tbsd -20 64fs 50 20 20 hz % ns ns control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 14 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 - 0 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf note 13. ??? lrck ? bick ?????????? note 14. ?` 300ns (scl rg ) g???? note 15. i 2 c-bus nxp b.v. ???
[AK4688] ms1420-j-00 2012/05 - 11 - ?????t 1/fclk tclkl vih tclkh mclk vil 1/fsn, 1/fsd, 1/fsq lrck vih vil tbck tbckl vih tbckh bick vil clock timing (normal mode) tlrb lrck vih bick vil tlrs sdto 50% dvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing lrck= lrck1, lrck2 bick= bick1, bick2
[AK4688] ms1420-j-00 2012/05 - 12 - lrck bick sdto tbsd tmblr 50% dvdd 50% dvdd 50% dvdd audio interface timing (master mode) tpd vil pdn tpdv sdto 50% dvdd vih power down & reset timing thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing
[AK4688] ms1420-j-00 2012/05 - 13 - ?^
? 3a??? AK4688 ????????`????` 2 (port1, port2) ?? port1 adc port2 dac ?`???`?`? port ??`?`?r ????? mclk 1(mclk2), lrck1 (lrck2), bick1 (bick2) ? mclk1 (mclk2) lrck1 (lrck2) ? port ????????? AK4688 adc ? pdn1 pin(or pwad bit) dac ? pdn2 pin(or pwad bit) ??`??` C????????? i 2 c ?``???? pdn1 pin= pdn2 pin = ?h? and pwad bit = pwda bit = ?1? ??B?? ( table 1 , table 3 ) h/w ?``???? pdn1 pin= pdn2 pin = ?h? ??B??? ( table 2 , table 4 ) ?B? ?`?r (msn pin = ?h?) mclk1 `?`?r (msn pin = ?l?) ? mclk1 (mclk2) lrck1 (lrck2) bick1 (bick2) ?? ?????`?B??? adc ?0? ?` dac pull down(vss) ???? ?`?r (msn pin = ?h?) mclk1 `?`?r (msn pin = ?l?) ? mclk1 (mclk2) lrck1 (lrck2) bick1 (bick2) ??`?B_? ? on ????r (pdn1 pin= ?l? ?h?) mclk1, lrck1, bick1 ? adc ?? `?B?? on ????r (pdn2 pin= ?l? ?h?) mclk2, lrck2, bick2 ? dac ??`?B? pdn1 pin pwad bit master mode: mclk1 slave mode: mclk1,lrck1 and bick1 adc stauts adc out l power down 0 h 0 power down 0 h 1 non-active power down 0 h 1 active power up adc output (: don?t care) table 1. system clock for adc (i 2 c bnb?b?bbb|b?bb?a? port1) pdn1 pin master mode: mclk1 slave mode: mclk1,lrck1 and bick1 adc stauts adc out l power down 0 h non-active power down 0 h active power up adc output (: don?t care) table 2. system clock for adc (h/w bnb?b?bbb|b?bb?a? port1) pdn2 pin pwda bit mclk2,lrck2 and bick2 dac stauts dac out l power down vss h 0 power down vss h 1 non-active power down vss h 1 active power up dac output (: don?t care) table 3. system clock for dac (i 2 c bnb?b?bbb|b?bb?a? port2) pdn2 pin mclk2,lrck2 and bick2 dac stauts dac out l power down vss h non-active power down vss h active power up dac output (: don?t care) table 4. system clock for dac (h/w bnb?b?bbb|b?bb?a? port2)
[AK4688] ms1420-j-00 2012/05 - 14 - ? / ?t??
? msn pin port1 ? / `?`?O? port2 ?`?`????? `?r? lrck1 pin bick1 pin ???`?`?r? lrck1 (lrck2) pin bick1 (bick2) pin ?? ( table 5 ) msn pin port1 (adc) bick1, lrck1 port2 (dac) bick2, lrck2 l input (slave mode) input (slave mode) h output ?l?(master mode) input (slave mode) table 5. master/salve mode port1(adc) ???
? ?`?r (msn pin = ?h?) ???? mclk1 ? cks1-0 bit cks pin ??? O? ( table 6 , table 7 ) adc mclk1, bick1, lrck1 o???`?B? cks1 bit cks0 bit clock speed 0 0 256fs 0 1 384fs 1 0 512fs 1 1 768fs (default) table 6. port1(adc) master clock control (master mode, i2c ?`` ) cks pin clock speed l 256fs h 768fs table 7. port1(adc) master clock control (master mode, h/w ?`` ) `?`?r (msn pin = ?l?) ???? mclk1, lrck1, bick1 ? mclk1 lrck1 ?????????? on ????r (pdn1 pin = ? ?) mclk1 lrck1 bick1 ? adc ??`?B? adc normal speed mode(fs = 32k ~ 48khz) ???? lrck1 mclk1 (mhz) bick1 (mhz) fs 256fs 384fs 512fs 768fs 64fs 32.0khz 8.1920 12.2880 16.3840 24.5760 2.0480 44.1khz 11.2896 16.9344 22.5792 33.8688 2.8224 48.0khz 12.2880 18.4320 24.5760 36.8640 3.0720 table 8. port1(adc) system clock example
[AK4688] ms1420-j-00 2012/05 - 15 - port2 (dac) ???
? ???? mclk2, lrck2, bick2 ? ?? (mclk2) ????? (lrck2) ????????? mclk2 ????`?? ? {??? mclk2, lrck2 ? bick2 ????? dac ????? ?B????? 0v ?R (typ) ? mclk2 lrck2 bick2 ???? B_?? on ????r (pdn2 pin = ? ?) mclk2 lrck2 bick2 ???`?B? dac ????`?O??N??? dfs1-0 bits ?? manual setting mode (acks bit = ?0?) ??? auto setting mode (acks bit = ?1?) ? 1. manual setting mode (acks bit = ?0?) acks bit = ?0? b* dac b2 manual setting mode b.b-bmbaba?bpb?b?bb?bkbtb?bb?b2 dfs1-0 bits b*.3obbab ( table 9 ) a? dfs1 bit dfs0 bit dac sampling speed (fs) 0 0 normal speed mode 32khz~48khz 0 1 double speed mode 64khz~96khz (default) 1 0 quad speed mode 128khz~192khz 1 1 not available - table 9. port2(dac) sampling speed (acks bit = ?0?, manual setting mode) lrck2 mclk2 (mhz) bick2 (mhz) fs 256fs 384fs 512fs 768fs 64fs 32.0khz 8.1920 12.2880 16.3840 24.5760 2.0480 44.1khz 11.2896 16.9344 22.5792 33.8688 2.8224 48.0khz 12.2880 18.4320 24.5760 36.8640 3.0720 table 10. port2(dac) system clock example (normal speed mode @manual setting mode) lrck2 mclk2 (mhz) bick2 (mhz) fs 128fs 192fs 256fs 384fs 64fs 88.2khz 11.2896 16.9344 22.5792 33.8688 5.6448 96.0khz 12.2880 18.4320 24.5760 36.8640 6.1440 table 11. port2(dac)system clock example (double speed mode @manual setting mode) lrck2 mclk2 (mhz) bick2 (mhz) fs 128fs 192fs 256fs 384fs 64fs 176.4khz 22.5792 33.8688 - - 11.2896 192.0khz 24.5760 36.8640 - - 12.2880 table 12. port2(dac) system clock example (quad speed mode @manual setting mode)
[AK4688] ms1420-j-00 2012/05 - 16 - 2. auto setting mode (acks bit = ?1?) acks bit = ?1? dac auto setting mode ???????`? mclk2/lrck2 ?? ?O? ( table 13 , table 14 ) `?? dfs1-0 bits ?o?? mclk2 dac sampling speed (fs) lrck2 512fs, 768fs normal speed mode 32khz~48khz 256fs, 384fs double speed mode 64khz~96khz 128fs, 192fs quad speed mode 128khz~192khz table 13. port2(dac) sampling speed (acks bit = ?1?, auto setting mode) lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs sampling speed 32.0khz - - - - 16.3840 24.5760 36.8640 44.1khz - - - - 22.5792 33.8688 - 48.0khz - - - - 24.5760 36.8640 - normal 32.0khz 8.192 12.288 44.1khz 11.2896 16.9344 48.0khz 12.288 18.432 88.2khz - - 22.5792 33.8688 - - - 96.0khz - - 24.5760 36.8640 - - - double 176.4khz 22.5792 33.8688 - - - - - 192.0khz 24.5760 36.8640 - - - - - quad table 14. ??? mclk= 256fs/384fs ? 32khz~96khz ???`????? ( table 15 ) 32khz~48khz ???`?? dr, s/n mclk= 512fs/768fs r????? mclk dr, s/n 256fs/384fs 102db 512fs/768fs 105db table 15. mclk ? dr, s/n vS (fs = 48khz) ?????3???? dac iir ??????? (50/15 p s ) i???`? dem bit = ?1? xk?r???????????? on r??`???? ?????? double speed mode (mclk2=256fs/384fs), quad speed mode (mclk2=128fs/192fs) ????? off ? O i 2 c ?``?? dac (dem bit) ?O?? ( table 16 ) dem bit de-emphasis filter 1 on 0 off (default) table 16. de-emphasis control (normal speed mode)
[AK4688] ms1420-j-00 2012/05 - 17 - ???? hpf adc dc ??????? hpf i? hpf fc ? fs=48khz r 1hz ??? ?? fs ?? |???|????????? port ?`????`?`???O?? port1 dif1 bit potr2 dif21-20 bits O???`?? msb ?`? 2?s compliment ?`?`???? sdto bick1 ?? sdti bick2 ???? sdti ?`?? ??`? lsb ? ?0? 1. port1(adc) w
? msn pin, dif1 bit ?? 4 N?`?`???xk?? ( table 17 ) lrck1 bick1 mode msn pin dif1 bit sdto l/r i/o speed i/o 0 l 0 24/16bit left justified h/l i 48fs or 32fs i (default) 1 l 1 24bit, i 2 s l/h i 48fs i 2 h 0 24bit left justified h/l o 64fs o (default) 3 h 1 24bit, i 2 s l/h o 64fs o table 17. audio inte rface format (adc) 2. port2(dac) w
? dif21-20 bit ?? 4 N?`?`???xk?? ( table 18 ) lrck2 bick2 mode dif21 bit dif20 bit sdti l/r i/o speed i/o 0 0 0 16bit, right justified h/l i 32fs i 1 0 1 24bit, right justified h/l i 48fs i 2 1 0 24bit, left justified h/l i 48fs i (default) 3 1 1 24bit, i 2 s l/h i 48fs i table 18. audio inte rface format (dac)
[AK4688] ms1420-j-00 2012/05 - 18 - lrck bick(64fs) sdto(o) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti(i) 1 14 0 15 8 7 1 14 0 15 8 7 lch data rch data don?t care don?t care 12 11 10 sdto-23:msb, 0:lsb; sdti-15:msb, 0:lsb figure 4. port1= mode0/2, port2=mode0 timing lrck bick(64fs) sdto(o) 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti(i) 1 22 0 23 8 7 1 22 0 23 8 7 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 5. port1= mode0/2, port2=mode1 timing lrck bick(64fs) sdto(o) 0 1 2 21 22 23 24 31 0 1 2 0 23 1 22 1 23 22 23 sdti(i) 22 23 0 22 23 23:msb, 0:lsb lch data rch data don?t care 2 2 1 28 29 30 23 0 22 23 24 31 1 0 don?t care 2 21 28 29 30 0 figure 6. port1= mode0/2, port2=mode2 timing lrck bick(64fs) sdto(o) 0 1 2 3 22 23 24 25 0 0 1 sdti(i) 31 29 30 23 22 1 22 23 0 23:msb, 0:lsb lch data rch data don?t care 2 2 1 0 2 3 22 23 24 25 0 31 29 30 23 22 1 22 23 0 don?t care 2 21 0 1 figure 7. port1= mode1/3, port2=mode3 timing
[AK4688] ms1420-j-00 2012/05 - 19 - pre-amp ?q?? att AK4688 ? (lin/rin) ? (ri) li/ri pin lo/ro pin g??? (rf) ????? att ????? ( figure 8 ) lo/ro pin ??R typ. 1.91vrms ?????? (lin/rin) ??? ri ??R 2vrms 4vrms ?^ ?? ri rf ^ typ. 1.91vrms ?p??? table 19 ri rf ? ? lin li lo pre-amp ri r f figure 8. pre-amp and input att ? ???O input range ri (k ? ) rf (k ? ) att gain (db) lo/ro pin adc output (typ) 4vrms 47 20 -7.42 1.70vrms -1.0dbfs 2.2vrms 47 39 -1.62 1.82vrms -0.39dbfs 1vrms 47 82 +4.83 1.74vrms -0.78dbfs table 19. input att example
[AK4688] ms1420-j-00 2012/05 - 20 - ????s? dvdd pin ?o??R?`?????? (cvee) ??? ???????????? `???`??rg? 1.3msec@48khz (typ) ??? adc dac ?` ?????? `???? i 2 c ?``???Q???? ? pdn1 pin=?h? pwad bit = ?1? mclk1, lrck1, bick1(master mode r mclk1) ?r ? pdn2 pin= ?h? pwda bit = ?1? mclk2, lrck2, bick2 ?r h/w ?``???Q???? ? pdn1 pin= ?h? mclk1, lrck1, bick1(master mode r mclk1) ?r ? pdn2 pin= ?h? mclk2, lrck2, bick2 ?r pdn1 pin pwad bit master mode : mclk1 slave mode : mclk1,lrck1, bick1 pdn2 pin pwda bit mclk2, bick2, lrck2 cp status h 1 active x x on x x h 1 active on (: don?t care) table 20. charge pump power on (i2c ?`` ) pdn1 pin master mode: mclk1 slave mode: mclk1, lrck1, bick1 pdn2 pin mclk2, bick2, lrck2 cp status h active x on x h active on (: don?t care) table 21. charge pump power on (h/w ?`` ) dvdd charge pump cp cn vss3 vee 1uf 1uf negative power a k4688 (+) cb ca (+) figure 9. ??? ? : cp-cn g dvss-vee g 1uf esr ?????
[AK4688] ms1420-j-00 2012/05 - 21 - ???? z? (lin/rin, lout/rout pins) ??i`??????? avss2 (0v) ?? ????????? dc ??????????? 5k (min) ? dac 0dbfs r?R 2vrms (typ) ? v 1?????; dac ??????`?????g? smute bit ?1? ? normal speed mode ? 1024lrck ?` - (?0?) ????`??? smute bit ?0? ?? - ?B? - 1024lrck 0db ??????`_?? 1024lrck ?????`??? 0db ??????` C???????????? smute bit attenuation 1024/fs 0db - ? : (1) normal speed mode ?? 1024lrck (1024/fs) ?` - (?0?) ????` ? double speed mode ?? 2048lrck (2048/fs) quad speed mode ?? 4096lrck (4096/fs) ?` - (?0?) ????`??? (2) ??????W (gd) ?? (3) ???`_?? 1024lrck ? normal speed mode ????? `??? 0db ??? figure 10. bxb?b?b?b?bb??(? v 3a??? pdn1 pin = pdn2 pin = ?l? ?B??????? (dvdd, avdd1, avdd2) ?? pdn1 pin pdn2 pin ?l? : ?h? ? ??? (pdn1 pin = ?l? : ?h? pdn2 pin= ?l? : ?h?) ??????`?B?? pdn1 pin pdn2 pin ???? ????`?????? pdn1 pin ?l? ??? adc ? ???? adc ??`? (addr: 01h ? 02h) pwad bit ???? pdn2 pin ?l? ??? dac ????? dac ??`? (addr: 03h) pwda bit ???? pdn1 pin pdn2 pin I ?l? ????????`? ????`???`??? h/w ?`r??o? pdn1 pin pdn2 pin ??`???`?????
[AK4688] ms1420-j-00 2012/05 - 22 - ????~??; AK4688 adc ????`? (pdn1 pin) ?l? ???? dac ????` (pdn2 pin) ?l? ?????`???r??????? ? pdn1 pin = pdn2 pin = ?l? ??????``?r?? 0v sdto pin ?l? ????????r???? adc ??`???? pdn1 pin: ?l? ?h? ??`???? mclk1 ? ? ????`?? ????? `?`???? pdn1 pin: ?l? ?h? ??`???? mclk1, lrck1, bick1 lrck1 ? ? ??? ?`??????? dac pdn2 pin: ?l? ?h? ??`???? mclk2, lrck2, bick2 lrck2 ? ? ????`??????? adc ???``?_????` 2640 _? dac ???``?_?? ?? 0v ? figure 11 adc, dac ?r??`????`??r` ?? adc dac pwad bit pwda bit ?????`????? ? pwad bit = ?0? ? adc ?` ?l? ??? pwda bit = ?0? ??? 0v ??? a dc internal state clock in mclk1,lrck1,bick1 mclk2,lrck2,bick2 a dc in (analog) a dc out (digital) dac internal state dac in (digital) dac ou t (internal status) power-down don?t care gd ?0?data power-down ?0?data g d (5) (5) (6 ) timea init cycle normal operation (3) gd normal operat ion gd (4) ?0?data ?0?data don?t care (2) pdn1 pin = pdn2 pin power (1) (7) 0v cvee 0v cvee pin timeb (9 ) (8 ) 0v 80% avdd2 vrefp in figure 11. power-up/down sequence example
[AK4688] ms1420-j-00 2012/05 - 23 - ? (1) ??? pdn1 pin, pdn2 pin ?l? ? ?h? ?? ?? AK4688 ????? 150ns ? ?l? g?? pdn1 pin = pdn2 pin = ?l? ?B??????? (dvdd, avdd1/2) ??? pdn1 pin, pdn2 pin ?h? ?? (2) `???`? : pdn1 pin ?l? ? ?h? ? mclk1, bick1, lrck1 ? pdn2 pin ?l? ? ?h? ? mclk2, bick2, lrck2 cvee pin ?s 1.3msec@48khz(typ) rg cvee ?R?? ? ? :charge-pump ???g pwad, pwda bit ?1? O??? pdn1pin pdn2 pin ?h? O?? adc, dac charge-pump ??? ?? (3) adc ??`? adc ???? timea=528/fs (4) dac ??`? dac ???? vref pin 1 f ??? timeb Q???? timeb 6/fs82 : normal speed mode timeb 12/fs82 : double speed mode timeb 24/fs82 : quadruple speed mode timeb ?? d/a ???? (5) ??????????W (gd) (6) ?`r adc ?0? ?`? (7) `???` : (pdn1 pin = ?h? ? ?l? or mclk1, bick1, lrck1 o ) (pdn2 pin = ?h? ? ?l? or mclk2, bick2, lrck2 o ) cvee pin ????????? 0v ?????? 50k ? ? ? cvee pin ???? 1f rr 50msec (typ) ??? (8) `???? 2048/fs g? (9)adc/dac ?` vref ???s 5msec (typ) ?
[AK4688] ms1420-j-00 2012/05 - 24 - 3???????????? AK4688 i 2 c `??`?????` (max:400khz) ??? 1. ?`???? ? ic ????` ??? 1 ?? ?????` ???r? ic ???? ??^??? ic ??????? ic ? read ? write g?K?r???? ? 1-1. ?`? ? ?h? g? sda ?B????????` ?h? ?l? g? B??` ????? ?? scl ??? ? ?l? r?? scl sda data line stable : data valid change of data a llowed figure 12. data transfer 1-2. `??????? scl ?h? r sda ?h? ?l? ??` ???? ?` ?????? scl ?h? r sda ?l? ?h? ? ??? ??????? ??K?? scl sda stop condition start condition figure 13. start and stop conditions
[AK4688] ms1420-j-00 2012/05 - 25 - 1-3. ? ?`?? ic ? 1 ??`? sda ?? (high ?B? ) `? ic ?? sda ?l? ???????? ??`????_J?? AK4688 ?` ??` ????????? write ??????? ???? read ???? AK4688 ????A?? ??` sda ? sda ?`???? ? ?o??? AK4688 ????`?? ???? AK4688 ??`K?? scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge figure 14. acknowledge on the i 2 c-bus 1-4. first byte `????? 1 ??`???` ??? ? ic ic x?` ?? 7 ????? 6 ?? ?001001? ?? 1 ???? ic x????? (cad0 bit) ? cad0 pin O?? cad0 bit O? (cad0 pin = ?l?: cad0 bit = ?0 ?, cad0 pin =h?: cad0 bit= ?1?) ` ???????? ic ??? g? 1 ? 8 ??? ( ?? ) r/w bit ? r/w bit= ?1? ? read ?g? r/w bit= ?0? ? write ?g? 0 0 1 0 0 1 cad0 r/w figure 15. the first byte
[AK4688] ms1420-j-00 2012/05 - 26 - 2. write r/w bit ?0? ?? AK4688 write ? write ??`???? ?? 2 ??? 2 ???`???? ?? msb first ? 3 ??? don?t care ? * * * a4 a3 a2 a1 a0 (*: don?t care) figure 16. the second byte 2 ??? 3 ??? 3 ??`?`? ??`?` 8 ??? msb first ?? d7 d6 d5 d4 d3 d2 d1 d0 figure 17. byte structure after the second byte AK4688 }??`???z???? 3 ?? ?`?????? ??o??`????? ??????????`????{??? 03h ?? ` `?`??? 00h ??{? sda s t a r t a c k a c k s slave a ddress a c k register a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) figure 18. write operation
[AK4688] ms1420-j-00 2012/05 - 27 - 3. read r/w bit ?1? ?? AK4688 read ??????`??? ?? ??o??????`i?? ???? 03h ?`i?????i?????? 00h ?`i?? AK4688 ? ?? `?? `?? read ???? 3-1. ????` AK4688 ???? ?????? ?? `??????? ???`i????? ???????? ??????? (read ? write ? ) ?? ?n? ?? ?? `????? ?n+1? ?`i?? ?? `??? AK4688 read ` ?? (r/w bit = ?1?) ???? ???? ?????`??? 1 ??? ?? 1 ??`??????? ? ?? read ?K?? sda s t a r t a c k a c k s slave a ddress a c k data(n) data(n+1) p s t o p data(n+x) a c k data(n+2) figure 19. current address read 3-2. ?` `?????`i???? `? read ` ?? (r/w bit = ?1?) ???` write ?? `???` ? write ` ?? (r/w bit = ?0?) i????? AK4688 ???????? ` ? read ` ?? (r/w bit = ?1?) ? AK4688 ? ` ???????????`??? ?? 1 ??????`??????? ??? read ?K?? sda s t a r t a c k a c k s s s t a r t slave a ddress word a ddress(n) slave a ddress a c k data(n) a c k p s t o p data(n+x) a c k data(n+1) figure 20. random read
[AK4688] ms1420-j-00 2012/05 - 28 - ?? addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h powerdown/control 0 0 0 0 0 0 pwda pwad 01h (reserved) 0 0 0 0 0 0 0 0 02h adc clock 0 0 0 dif1 0 cks1 cks0 0 03h dac clock 0 acks dfs1 dfs0 dem dif21 dif20 smute ? : ?? 04h 1fh ?z??? pdn1 pin pdn2 pin ?l? ???????? pdn1 pin ?l? ?? adc ??`??? adc ?? (addr: 01h-02h) pwad bit ??? pdn2 pin ?l? ?? dac ??`??? dac ?? (addr: 03h) pwda bit ? ?? pwad bit ?0? ?? adc ??`??? adc ?? (addr: 01h-02h) ? ?? pwdabit ?0? ?? dac ??`??? dac ?? (addr: 03h) ?? ? ???? ?0? bit ? ?0? z?
[AK4688] ms1420-j-00 2012/05 - 29 - ?i
? addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h powerdown/control 0 0 0 0 0 0 pwda pwad r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 0 0 0 pwad: adc ?`???` 0: power-down(default) 1: normal operation pwda: dac ?`???` 0: power-down (default) 1: normal operation addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h (reserved) 0 0 0 0 0 0 0 0 r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0
[AK4688] ms1420-j-00 2012/05 - 30 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h adc clock 0 0 0 dif1 0 cks1 cks0 0 r/w rd rd rd r/w rd r/w r/w rd default 0 0 0 0 0 1 1 0 cks1-0: master mode r port1(adc) ??` table 6 ? dif1: port1 `??`??xk table 17 ? addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h dac clock 0 acks dfs1 dfs0 dem dif21 dif20 smute r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 1 0 0 0 1 0 0 smute: soft mute control for dac 0: normal operation (default) 1: lout/rout outputs soft-muted dif21-20: port2 `??`??xk table 18 ? dem: dac ?????` table 16 ? dfs1-0: port2(dac) ????`??` table 9 ? auto setting mode (acks bit = ?1?) ? dfs1-0 bits O?o?? acks: port2(dac) `?????`??` 0: o , manual setting mode 1: ? , auto setting mode (default) acks bit= ?1? ? mclk ?????? dfs1-0 bits O?o ?? acks bit= ?0? ?????`?`? dfs1-0 bits O `?? mclk ?????
[AK4688] ms1420-j-00 2012/05 - 31 - 3a
?- figure 21 ???A????y???u??` (akd4688) ? AK4688en audio dsp1 analog in 1 sdto 2 lrck1 7 mclk2 8 bick2 9 lrck2 36 msn 35 scl 34 sd a 33 i2c 32 lin 31 nc 30 rin 29 li 28 lo 10 sdti 12 test1 13 test2 14 dvdd 15 dvss 16 cp 17 cn 18 cvee 27 ro 26 r1 25 avdd1 24 avss1 23 avss2 22 avdd2 21 vref 20 lout 19 rout 3 bick1 4 mclk1 5 pdn1 6 pdn2 reset and power down audio dsp2 micro controller 47k 47k analog out 39k 39k 11 cad0 3.3v 1u 0.1u + ( ? ) 1u ( ? ) 3.3v + 10u 0.1u + 10u 0.1u 1u ( ? ) 3.3v 3.3v 3.3v figure 21. ??A (i 2 c control mode, cad0 pin = ?l?, master mode) notes: (1) (*) ?? esr ??????O??????? cp, vref O?? cvee ?O???A? (2) avss1, avss2, dvss ???????A (3) ???`????
[AK4688] ms1420-j-00 2012/05 - 32 - AK4688en audio dsp1 analog in 1 sdto 2 lrck1 7 mclk2 8 bick2 9 lrck2 36 msn 35 scl 34 sd a 33 i2c 32 lin 31 nc 30 rin 29 li 28 lo 10 sdti 12 test1 13 test2 14 dvdd 15 dvss 16 cp 17 cn 18 cvee 27 ro 26 r1 25 avdd1 24 avss1 23 avss2 22 avdd2 21 vref 20 lout 19 rout 3 bick1 4 mclk1 5 pdn1 6 pdn2 reset and power down audio dsp2 47k 47k analog out 39k 39k 11 cad0 1u 0.1u + ( ? ? ? figure 22. ??A (h/w control mode, mclk=768fs, master mode) notes: (1) (*) ?? esr ??????O??????? cp, vref O?? cvee ?O???A? (2) avss1, avss2, dvss ???????A (3) ???`????
[AK4688] ms1420-j-00 2012/05 - 33 - 1. ????q?ow????? ?????????? avdd1, avdd2, dvdd ????? ??????o? avdd1, avdd2, dvdd e??o???? ?`??????? avss1, avss2, dvss ????? ???A ????????? pc ?`?? ???A???????????????A 2. , j?y avdd1 avss1 ?R?????O? avdd2 avss2 ?R??? ??O? vref ??????R???????? ? 1 f ????? avss1/avss2 ?g??A verf pin ?? ??????????{???????? vref pin ? x 3. ????? AK4688 ??????l pre-amp ???????? ???? pre-amp adc(lo, ro pin) (typ. 1.91vrms) ??? feedback ?{ `??`??? 2?s ??? dc ?? (adc dc ? ?? ) i hpf ????? AK4688 64fs ?????????? ??? 64fs ??????? AK4688 64fs p???????? (rc ?? ) i?? 4. ??? z? ?????????????? avss2(0v,typ) ? 2.0vrms(typ, @avdd2=3.3v) ?i ? {k? ( `??? ) i? ??? (scf) BA?? (ctf) p??}????g 1 lpf( figure 23 ) `??`??? 2?s complement (2 a ) 7fffffh(@24bit) ????`? 800000h(@24bit) ?????`? 000000h(@24bit) ? v l/rout ? 0v(vss) ? dc ??? 5 v ? l/rout 470 2.2nf AK4688 2.0vrms (typ) analog out (fc = 154khz, gain = -0.28db @ 40khz, -1.04db @ 80khz) figure 23. external 1 st order lpf circuit example 5. , x
w?? lin, rin pin pre-amp ???`???????????????? ????? li, ri pin ???????? feedback ? ??L??? lin, rin pin ?????????` ?
[AK4688] ms1420-j-00 2012/05 - 34 - ?-? 36pin qfn (unit: mm) $ "# . # $."9 $ " p~y???7 ??`| ????????c??` `??`| ~ `??`I? ( oU ) ?
[AK4688] ms1420-j-00 2012/05 - 35 - ???? 4688 xxxx 1 pin #1 indication date code: xxxx (4 digits) ~do date (yy/mm/dd) revision reason page contents 12/05/29 00
[AK4688] ms1420-j-00 2012/05 - 36 - ?? z ?d?u??u???????u????? ??????H???dQ????I ???s?I?_J z ?d?x????vB??u?? h??CO????d?x? ??vB????????? ?d?x????vB?????? ??p? ?????? ? ?????? I?????????? z ?du??Q???Y???????? H????S??? z ?C??C? C???C?? ??g???]?b???p????????O? m??????u???????????? ?? z ?????u????????p?? ??????? z ??????????o???u??????p ?????????a????

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